Intel shows off new 22nm wafer
IDF 2009: Intel chief executive Paul Otellini shows off a silicon wafer housing chips made with 22nm process technology
IDF 2009: Intel chief executive Paul Otellini shows off a silicon wafer housing chips made with 22nm process technology
At the Intel Developer Forum in San Francisco, Intel's Justin Rattner and Michael Garner talk about materials and processes that will be used in the next 40 years to increase chip performance and advance production. Rattner and Garner discuss the future use of CMOS (complementary metal oxide semiconductor) technology and carbon-based devices such as carbon nanotubes.
At the Gartner Symposium/ITxpo in Las Vegas, David Douglas of Sun Labs shows off a new technology the company is developing inside its labs called "Proximity Communications." The new chip process will allow faster application speeds for high performance computers.