Researchers at Stanford University have built the first three-dimensional carbon nanotube circuits with a new technique that stacks multiple layers of nanotubes on top of one another.
First, researchers had to tackle the endemic short-circuit-causing problems of nanotubes, which resemble microscopic tangles of straw-shaped webs. Until now, engineers have had difficulty stringing together nanotube transistors, millions of which are required to emulate a microprocessor or memory chip.
The researchers used three techniques -- two existing, one new -- to overcome the problems: the first, invented in 2007, allows transistors to work regardless of whether the component nanotubes lie perfectly straight; the second, invented in 2008, enables VLSI-scale fabrication of nanotube transistors on a chip; the third, announced this month, removes problematic "metallic" nanotubes that conduct electrical current even when they are not supposed to without damaging "healthy" nanotubes around them.
The new technique is called "VLSI-compatible Metallic Nanotube Removal," and breaks up troublesome nanotubes by exposing them to high current using a grid of electrodes that can then be etched to produce any circuit design.
"This body of work illustrates that carbon nanotube transistor technology has moved beyond the realm of scientific discovery and into engineering research," said Stanford professor and paper co-author H.S. Philip Wong in prepared remarks. "We are now able to construct devices and build circuits on a wafer scale."
To fashion a three-dimensional cabon nanotube circuit, Stanford researchers used a low-temperature process in which nanotubes are transferred from a quartz wafer to a silicon chip.
Technology Review explains the process:
To make a three-dimensional circuit, the researchers simply repeat the stamping and electrode-growth procedures to stack as many layers as are needed before the final etching process. The nanotube stamping process, which the Stanford group first demonstrated last year, is key to creating stacked layers because it can be done at low temperatures that don't melt the metal electrical contacts in underlying layers.
The prototype is a three-layer chip with dozens of nanotube transistors connected in functioning logic gates by nanotube-and-metal wiring. With five to 10 nanotubes per micrometer, the chip yields a higher density of connections among layers that previous circuits.
The next challenge? Increasing the density of nanotubes per micrometer. In a decade's time, the chips could help pave the way for faster, cheaper, more energy-efficient computers.
The researchers presented their results at the International Electron Devices Meeting in Baltimore.